This invention relates generally to the field of clocking circuits and more particularly relates to increasing the timing margin of a clock signal throughout a clocked system by adjusting clock control settings relative to clock frequency.
In order for electronic systems such as computers and computer memory devices to operate properly and reliably, the timing specifications of each integrated circuit in the system must be thoroughly characterized and guaranteed. Manufacturers of integrated circuits of semiconductor devices categorize these circuits by speed grade which designates the preferred speed for proper operation. Ideally, the manufacturer tests each integrated circuit as it is produced. If the integrated circuit passes the timing requirements for the targeted speed grade, it is sold at the corresponding prices; typically the price of a circuit increases with the operating speed of the circuit. If the integrated circuit fails, it may be down-graded to a lower speed grade and sold for a lower price.
In order to meet the requirements of a particular speed grade the integrated circuit must meet several different timing specifications. For example, consider a system of many integrated circuits in which a digital logic signal, typically a square wave, is transmitted on common bus between two integrated circuits controlled by a common clock. For proper communication it is critical that the signal arrive at the receiving integrated circuit no later than a specified time, sometimes on the order of hundreds of picoseconds, after a relevant edge, e.g., the rising edge, of a previous clock signal. This specified time or margin allows the semiconductor devices to stabilize and correctly receive the input signal before the next edge of interest which may be a rising or a falling edge of the clock when the data is latched by the receiving integrated circuit. Similarly, the integrated circuit transmitting the logic signals must continue to provide the data to the receiving circuit for a specified time after the rising edge of the first clock signal. This ensures that the receiving circuit has completely latched the input signal before the signal is removed from the bus.
Generally, clock signals toggle as fast as or faster than any other signals in a digital processing system. For every data transition, a clock must undergo two transitions. Not only are clocks the fastest signals, they are also the most heavily loaded because clocks are connected to every latch in a system whereas individual data wires fan out to relatively only a few integrated circuits. In order for a clock signal to propagate through a system, it is preferable that the timing margin be as large as possible given faster and faster clock frequencies. The timing margin measures the slack or the excess time remaining in each clock cycle after it has received a logic signal. The timing margin depends on both the delay of logic paths and the clock interval. Too short a clock interval can cause a timing margin failure.
Typically, during testing and during initial program load, various tests are run on the functions on the microprocessor and memory nest integrated circuits. These tests include Logic/Array Built-In-Self Tests (LBIST and ABIST). These are dynamic frequency tests that are run at chip and module level to test the operating frequency of logic and arrays. It is suggested to never operate a circuit near its failure frequency, especially if there is minimal timing margin. It is always preferable to reduce the maximum operating speed for any circuit somewhat below the frequency at which the tests fail, leaving a small positive timing margin under all operating conditions. A positive timing margin protects the integrated circuits against signal crosstalk which perturbs the edge transition times, general miscalculations that often occur when counting logic delays, and later minor changes in the circuit card design or layout.
Several components affect the timing margin; one such is the clock skew which can be considered as the maximum difference in the arrival time of the clocks between any two latches or flip-flops. The skew can be positive or negative depending upon the routing direction and the position of the clock source. Quite simply, the clock period between any two latches must be large enough for the data to latch or the computations to settle. Another aspect of the timing margin is the clock jitter. Jitter refers to the change in the timing of the clock from period to period. Temperature affects jitter as when an oscillator warms, it may gradually change in frequency, voltage, and or phase. Other factors affecting skew and/or jitter are the impedance of the distribution lines, the impedance of the clock drivers, the crosstalk between two signal lines, delays, etc.
An important concept is the duty cycle which is considered as the time a signal is in its high state divided by the signal""s period. An ideal duty cycle for a clock signal is fifty percent, i.e., the falling edge of the ideal clock signal precisely bisects successive rising edges so that the average voltage of the ideal clock lies halfway between its high and low states. The symmetry of a clock signal is another way of looking at the duty cycle; if the clock signal is symmetrical, then its period is equally divided between its high voltage, Vdd, and its low voltage, typically ground, and the amplitude of the high voltage is as much above a reference voltage as the low voltage is below the reference voltage. But clocks become unbalanced drifting away from a fifty percent duty cycle because circuit elements have an asymmetric response to the rising and falling voltages of the waveforms. Indeed, it has been discovered that some technologies and some circuits, such as silicon-on insulator and copper, are sensitive to either one or the other of the rising or falling waveforms and therefore a duty cycle other than fifty percent is deemed desirable.
A microprocessor, a bus arbitration logic unit, a memory controller or other computer circuits typically have a phase locked loop (PLL), a Digital Multiplier (DM), or a Symmetry Correction Circuitry (SCC) to generate the clock for the chip. These circuits may have inputs that can be adjusted to change characteristics of the generated clock signal. Typically, adjusting these clock settings is done by measuring and characterizing a few systems using a service processor and then using the same inputs for each system or clock. This may be very well and good when a system operates at only one frequency or at only one operating voltage but today""s systems can operate at faster frequencies and lower voltages. Systems today, moreover, are expected to operate at more than one frequency and at more than one operating voltage or at least accommodate connections to other systems that operate at different voltages and frequencies.
There thus is an increasing need for a dynamic method to adjust clock control settings at different operating frequencies and at different operating voltages to adjust the timing margin of a clocked integrated circuit for particular applications.
This need has been be a method of optimizing the performance of an electronic system controlled by a clocked frequency, comprising the steps of: setting a frequency of a clock to a default; setting each of a plurality of clock control factors to a default parameter; running a test of the electronic system; incrementing the frequency and rerunning the test until the test fails; then changing at least one clock control factor and then incrementing the frequency and rerunning the test until the test fails; again, upon failure of the test, readjusting at least one clock control factor and repeating the cycle of incrementing the frequency, rerunning the test until the test fails, adjusting at least one clock control factor until a desired timing margin of the clock is achieved.
Setting each of the plurality of clock control factors to a default parameter may further comprise initializing one or more of the following default parameters of a phase-locked loop: the voltage gain of a voltage controlled oscillator within the phase-locked loop; current gain of the voltage controlled oscillator; range of the voltage controlled oscillator; the charge pump current; the damping factor; the gain of the phase detector; or the bandwidth. If a digital multiplier or a symmetry correction circuit is used to generate a clock, the step of setting a clock control factor to a default parameter may comprises setting the duty cycle.
The electronic system may comprise an array of semiconductor memory in which an ABIST test may be performed on the memory array. If the electronic system comprises digital logic circuits, an LBIST test may be performed on the digital logic circuits. In any event, where the electronic system comprises a clock distribution network, a semiconductor memory array, and digital logic circuits, functional tests may be performed.
The method of optimizing the performance as outlined above may be performed automatically for the clocked digital system in which a desired timing margin is preset, or the clock control settings and frequency can be manually adjusted to obtain a desired timing margin.
The invention is further embodied in an automated method of obtaining a desired timing margin of a clock in a clocked electronic system having a plurality of circuits, with the method comprising the steps of: inputting the desired timing margin; setting a default frequency; setting each of a plurality of clock control factors to a default parameter; generating a clock signal having the default frequency and default parameters; running a functional test of the clocked electronic system; incrementing the frequency; rerunning the functional test; and repeating the steps of running the functional test and incrementing the frequency until the test fails; if the clock signal is generating within a phase-locked loop (PLL), then the method further contemplates changing at least one of the following clock control factors: voltage gain of a voltage controlled oscillator within the PLL, current gain of the voltage controlled oscillator; range of the voltage controlled oscillator; the charge pump current, damping factor, phase detector gain, or bandwidth; if the clock signal is generated within a digital multiplier or a symmetry correction circuit, then upon failure of the test, the method contemplates adjusting the duty cycle of the clock signal; and then automatically repeating steps of incrementing the frequency and running the test until it fails at a particular frequency, then adjusting the clock control settings and then rerunning the test and incrementing the frequency, etc. until a desired timing margin and frequency of the clock is achieved.
The invention further is envisioned as an apparatus for controlling a timing margin of a clocked digital system, comprising a plurality of semiconductor logic and memory circuits; a means for generating a clock signal; a means to distribute the clock signal to the semiconductor logic and memory circuits; a means to test the semiconductor logic and memory circuits; a means to adjust the frequency of the clock signal; a means to adjust at least one clock control settings of the clock signal; and a means to adjust the timing margin based on results from the testing means with the frequency adjusting means and the clock control setting adjusting means.
The invention has been summarized, but will better be understood with reference to the Detailed Description of the Invention in conjunction with the Drawing in which: